1. Field of the Invention
The present invention relates to a clock switching circuit for switching and outputting a plurality of clocks having different phases, and more particularly to a clock switching circuit for switching a clock at a timing that is asynchronous with a switching subject clock.
2. Description of Related Art
QDR (Quad Data Rate) SRAM is SRAM capable of an ultra-high speed operation by separating a data input and a data output, which are constituted by a common terminal in typical SRAM, and performing reading and writing simultaneously while operating the data input and data output respectively at a DDR (Double Data Rate). With QDR SRAM, data transfer can be performed at a higher speed than with a conventional synchronous SRAM product, and therefore QDR SRAM is highly suited to sophisticated next-generation network switches, routers, and so on.
A clock switching circuit into which two True/Bar (hereafter, True: T and Bar: B) clocks having phases differing by 180 degrees are input as external clocks, and which is installed with two PLL circuits corresponding to the respective external clocks, is applied to this type of QDR product. The clock switching circuit is capable of switching between an external clock and a clock (PLL clock hereafter) output by the PLL circuit in accordance with a PLL enable signal.
FIG. 12 is a block diagram showing a peripheral circuit including a clock switching circuit used by a QDR product. A clock switching circuit 101 comprises PLL circuits 102, 103 having external clocks CLKT, CLKB as inputs, a transfer 116 for aligning delays, an inverter 115 for inverting an output PLT of the PLL circuit 102, a multiplexer 114 for selecting and outputting the output of the inverter 115 or the output of the PLL circuit 103, and multiplexers 144, 146 for switching between the externally input T/B clocks (CLKT, CLKB) and PLL output clocks (PTOUT, PBOUT) generated in a chip interior in accordance with a control signal (DLLE) from the outside of the chip. Clocks CKT, CKB output by the clock switching circuit 101 pass through clock trees 105, 109, respectively, and are supplied to resistors 121, 122, or the like for use in an internal circuit operation.
For a certain, fixed cycle period following power ON, the PLL circuit requires a waiting time (lockup time) for the output to stabilize. A state from input of a basic clock into the PLL circuit to stabilization of the output clock of the PLL circuit to a predetermined frequency is known as an unlocked state, and a stable state in synchronization with the predetermined frequency is known as a locked state. During the waiting time from the unlocked state to the locked state, the phase of the PLL outputs (PLT, PLB) may not correspond to T/B (180°) even when the T/B phases of the external clocks (CLKT, CLKB) reach 180°, and when this state occurs, problems such as malfunctions and through-currents occur in a subsequent circuit. Hence, the multiplexer 114 is provided so that a T side inverted clock (PLTB) can be used instead of using the PLL output of the B side clock (CLKB). The multiplexer 114 is capable of switching a Fuse or the like, for example, such that one of the outputs is selected and fixed. Note that the internal clock PTOUT is the output PLT of the PLL circuit 102.
In this type of clock switching circuit 101, the control signal (DLLE) is input asynchronously with the clock to be switched, and therefore the multiplexers 144, 146 are switched asynchronously. Further, when control is performed to switch to the output PLB of the PLL circuit 103 after the lockup time of the PLL circuit 103 without fixing the multiplexer 114, the lock detection timing is also asynchronous with PLB, and hence the multiplexer 114 is also switched asynchronously. When clock selection and switching is performed asynchronously with the selected and output clock in the multiplexers 114, 144, 146 in this manner, a short pulse (a glitch) occurs during switching, and this glitch affects the operations of the subsequent circuit. FIG. 13 shows a timing chart of a case in which a glitch occurs. As shown in FIG. 13, clock switching is performed at a timing at which the control signal DLLE is asynchronous with the external clocks CLKT, CLKB and the PLL outputs PLT, PLB, and therefore a glitch occurs in the output clocks CKT, CKB, as shown by A.
In other words, there is a need for a circuit configuration in which a glitch does not occur in a subsequent output clock during switching even when switching from an external clock to an internal clock is performed asynchronously using an external control pin (DLLE) or switching from a T side inverted signal to a B side clock is performed before and after lockup of a PLL circuit.
Incidentally, the following publications are well known as conventional clock switching circuits. First, Japanese Unexamined Patent Application Publication No. 2004-240818 (Kubota) discloses a clock generation circuit that avoiding a long-term stoppage in clock output without adding circuit for oscillating an auxiliary oscillator, and with which a normal operation of a subsequent circuit is achieved even when a short-period lock release occurs in a PPL circuit. FIG. 14 is a block diagram showing the clock generation circuit described in Kubota. FIG. 15A is a timing chart showing the generation of an extremely short pulse in an output clock 201g when a selector circuit 215 is not provided with an input 203. FIG. 15B is a timing chart showing a condition in which an extremely short pulse is not generated in the output clock 201g when the selector circuit 215 is provided with the input 203.
As shown in FIG. 14, a clock generation circuit 210 comprises a PLL circuit 211, a lock detection circuit 212, a counter circuit 213, a selector control circuit 214, and the selector circuit 215. The clock generation circuit 210 further comprises an input terminal 210A into which an input clock 201a is input, and an output terminal 215D for outputting the output clock 201g, which is output by the selector circuit 215. The output terminal 215D of the clock generation circuit 210 is connected to a clock input terminal 216A of a logic circuit 216.
The input clock 201a is input into the input terminal 210A of the clock generation circuit 210, and the input clock 201a is input into a clock input 211A of the PLL circuit 211. The PLL circuit 211 outputs a high speed clock obtained by multiplying the frequency of the input clock 201a as a PLL clock 201b from a multiplied clock output 211B to an input 201 of the selector circuit 215 and a comparative signal input 212B of the lock detection circuit 212.
The lock detection circuit 212 compares the phase of the input clock 201a input into a reference signal input 212A with the phase of the PLL clock 201b input into the comparative signal input 212B to determine whether the PLL circuit 211 is in an unlocked state or a locked state, and outputs an unlock signal 201c indicating the determination result from an unlock output 212C. The unlock signal 201c is active when the PLL circuit 211 is in an unlocked state and the lock is released. The unlock signal 201c output by the lock detection circuit 212 is input into an enable input 213A of the counter circuit 213 and a condition input 221 of the selector control circuit 214.
In the counter circuit 213, the period during which the PLL circuit 211 is in an unlocked state (a lock released state) is counted by counting an active period during which the unlock signal 201c indicates the aforementioned unlocked state. The unlock signal 201c is also input into the enable input 213A of the counter circuit 213, and during the active period of the unlock signal 201c, a counting operation is executed by the input clock 201a connected to a clock input 213B. When the unlock signal 201c becomes non-active, the count value is returned to its initial value.
Further, the selector circuit 215 leads one of the PLL clock 201b input into the input 201, the input clock 201a input into an input 202, and a fixed value “0” serving as a logical value input into an input 203 selectively to an output 215D on the basis of a value of a select signal 201f input into a select input 215E.
A select output 214B of the selector control circuit 214 is connected to the select input 2415E of the selector circuit 215, and the select signal 201f is input into the select input 215E from the select output 214B. As will be described below, when switching between the input 201 and the input 202 in the selector circuit 215, or in other words when switching between the PLL clock 201b and the input clock 201a having different periods, a malfunction in a subsequent logic circuit is prevented by first passing through the input 203 (fixed value 0).
In the clock generation circuit 210, if the selector circuit 215 switches the connection to the output 215D from the input 201 to the input 202 directly such that a phase deviation occurs between the PLL clock 201b (input 201) and the input clock 201a (input 202), as shown in FIG. 15A, an extremely short pulse is output to the output 215D as the output clock 201g, and this may cause a malfunction in the subsequent logic circuit 216.
On the other hand, by providing the input 203 in the selector circuit 215 such that switching between the input 201 and the input 202 is performed via the input 203, the output period of the fixed value 0 is interposed between the output period of the PLL clock and the output period of the input clock, as shown in FIG. 15B, and therefore generation of an extremely short pulse such as that of FIG. 15A can be prevented, thereby preventing a malfunction.
In other words, in the clock generation circuit 210, the selector circuit 215 is controlled by the select signal 201f from the selector control circuit 214. When the period during which the PLL circuit 211 is in the unlocked state exceeds a predetermined value, the input clock 201a is output instead of the PLL clock 201b. Hence, there is no need to add a circuit for oscillating an auxiliary oscillator, and as a result, frequent clock switching such as that of the related art can be avoided, and operations of a subsequent circuit can be stabilized.
Japanese Unexamined Patent Application Publication No. 2000-137699 (Ueno) discloses a microcomputer in which current consumption in an IDLE mode can be reduced and a time required to restore program execution by a CPU can be shortened when the IDLE mode is released. FIG. 16 is a block diagram showing the microcomputer described in Ueno. The microcomputer comprises an oscillation circuit 301, a PLL circuit 302, a frequency half divider 304, a first AND circuit 303, a second AND circuit 305, a selector 306, and an RS flip-flop 307.
In the oscillation circuit 301, terminals X1, X2 are connected respectively to terminals of an external crystal oscillator, for example, and grounded via a capacitor. The oscillation circuit 301 may be constituted by a crystal oscillation circuit comprising an inverting circuit and a feedback resistor connected in series between the terminals X1, X2, and a circuit for subjecting the output of the inverting circuit to waveform shaping and then outputting the waveform-shaped output. In a STOP mode, a STOP control signal serving as logical 1 is input. The STOP control signal serves as a control signal of a switch connected between one end of the feedback resistor and the terminal X1 or between the other end of the feedback resistor and the terminal X2, for example, and when the STOP control signal is logical 1, an oscillation operation is stopped by switching the switch OFF.
The PLL circuit 302 comprises a phase difference detection circuit into which a reference signal and a signal obtained by frequency-dividing the oscillation output of a voltage controlled oscillation circuit (VCO) using a frequency divider are input, a charge pump circuit, a loop filter, and the voltage controlled oscillation circuit. When the STOP control signal is logical 1, an oscillation operation is stopped by severing the path of a ring oscillator of the voltage controlled oscillation circuit, for example.
The frequency half divider 304 shapes the duty ratio of the output clock from the PLL circuit 302. The first AND circuit 303 inputs-an-inverted value of an IDLE control signal serving as logical 1 during an IDLE mode, and the output of the PLL circuit 302, and in the IDLE mode, when the IDLE control signal is logical 1, masks clock supply to an internal circuit without transmitting the output of the PLL circuit 302 to the frequency half divider 304. The second AND circuit 305 inputs an inverted value of a control signal taking a value of logical 1 while waiting for oscillation stability after the STOP mode has been released, and the output of the frequency half divider 304. From the STOP mode to the oscillation stabilization period following release of the STOP mode, the second AND circuit 305 masks the output of the frequency half divider 304 so that it is not transmitted to the internal circuit as an internal clock.
Further, an UNLOCK flag output from the PLL circuit 302 is a status flag indicating whether the PLL circuit 302 is in an unlocked state or a locked state, which is typically allocated to a status resistor or the like indicating the state of the PLL circuit 302. The locked state/unlocked state is detected in the PLL circuit 302 on the basis of the output of a phase difference detection circuit, and set in a status resistor within the PLL circuit 302.
A negative logic signal of the IDLE control signal serving as logical 1 in the IDLE mode is input into an S (set) input terminal of the RS flip-flop 307. A negative logic signal of the UNLOCK flag output from the PLL circuit 302 is input into an R (reset) input terminal. An output Q is used as a switching signal of the selector 306. The selector 306 is supplied with a clock (pre-multiplication clock) of the oscillation circuit 301 and a clock that is frequency-divided by the frequency half divider 304 after the output of the oscillation circuit 301 is multiplied by four in the PLL circuit 302, and selects and outputs one of these clocks. In other words, when the aforementioned switching signal is logical 0, the output of the second AND circuit 305 is selected and output, and when the switching signal is logical 1, the output of the oscillation circuit 301 is selected and output.
In a clock switching multiplexer for a low power consumption processing device described in Japanese Unexamined Patent Application Publication No. 2001-202155 (Kameya et al.), control is performed during switching of high speed and low speed clocks to apply an appropriate delay to the switching timing of a switching signal such that switching is performed when the high speed and low speed clock levels are both stable at a high level.
Further, in a clock switching circuit described in Japanese Unexamined Patent Application Publication No. 7-38398 (Arai), the generation of a glitch is prevented by shifting the switching timing of a first clock and a second clock obtained by frequency-dividing a master clock to a predetermined logical value of the corresponding clock.
However, in the technique described in Kubota, clock switching is performed by fixing the output clock to “0” during switching (201f select signal [1:0.] is in a state of 01), and therefore frequency variation during switching increases (see FIG. 17). Furthermore, in Kubota, when switching the two clocks having 180° differing phases in relation to T/B from the T side inverted signal to the B side clock while the PLL circuits are both in a locked state, a glitch is generated in the B side clock, possibly leading to instability in the operation of a subsequent circuit.
Further, in the technique described in Ueno, the switching timing is constituted by the RS flip-flop 307, and therefore clock switching is performed immediately upon reception of variation in the unlock flag. As a result, a short convex pulse may be generated during switching. Furthermore, when the T/B switching described above is implemented, the respective T/B clock signals do not have 180° differing phases during the period lasting until locking by the PLL circuit 302. In other words, the phase difference does not reach 180°, and therefore the subsequent circuit becomes unstable, leading to problems such as the output data becoming unknown data and a through-current flowing temporarily in the output resistor, for example.
Further, in the technique described in Kameya et al., the two clocks that are switched (the high speed clock and the low speed clock) are frequency-multiplied clocks, and the Rise edge/Fall edge of the switching subject clocks are aligned. In other words, when the Rise edge/Fall edge of the switching subject clocks are not aligned, as in the clock switching circuit shown in FIG. 12, a glitch is generated in the manner described above.
Furthermore, in the technique described in Arai, although a glitch is not generated during switching, frequency variation occurs during clock switching. In other words, the clock switching circuit described in Arai has flip-flops (FF) operated respectively by the falling and rising of the master clock, and the clocks are switched by controlling a selection circuit in accordance with the output of these FFs. However, a period during which neither of the clocks is selected occurs, leading to the generation of a low level fixed interval corresponding to the half period of the master clock, which appears in the output CLK.